This invention relates to a packet-switched system, as might be used in an ethernet system, and more particularly to using multiple spread-spectrum channels to achieve a high processing gain and maintain a high capacity channel.
For a given bandwidth, processing gain and power level, spread-spectrum communications systems have a limited capacity for communicating information over a single channel. Consider the T1 network and T3 network, by way of example, and assume a spread-spectrum transmitter spread-spectrum processes the message data at a rate of 25 megachips per second. For the T1 network which communicates data at up to 1.544 megabits per second, a typical processing gain of 17 might be realized. For the T3 network, which can have data rates of 10 megabits per second, a processing gain of 2.5 might be realized. The low processing gains can result in channel degradation and loss of the advantages of spread-spectrum modulation such as resistance to fading caused by multipath and ability to share the spectrum with other spread-spectrum systems.
A general object of the invention is a packet-switched system having high processing gain and high capacity.
Another object of the invention is a packet-switched system having sufficient processing gain using orthogonal chip sequences.
An additional object of the invention is a packet-switched system having fast acquisition and synchronization, and low cost.
According to the present invention, as embodied and broadly described herein, a packet-switched system is provided comprising a plurality of packet transmitters that communicate with a plurality of packet receivers using radio waves. Each of the packet transmitters includes a transmitter-first-in-first-out (transmitter-FIFO) memory, an encoder, a demultiplexer, chip-sequence means, a plurality of product devices, a combiner, a header device, and a transmitter subsystem. Each packet receiver includes a translating device, a header-matched filter, a processor, a plurality of data-matched filters, a multiplexer, a decoder, and a receiver-first-in-first-out (receiver-FIFO) memory.
In the packet transmitter, the transmitter-FIFO memory stores data from a data input. The encoder encodes the data from the transmitter-FIFO memory as encoded data. By the term xe2x80x9cencoderxe2x80x9d for encoding data from the transmitter-FIFO memory is meant privacy type of encoding, such as scrambling or encrypting the data. The term xe2x80x9cencoded dataxe2x80x9d as used herein is meant to include scrambled data or encrypted data. The demultiplexer demultiplexes the encoded data into a plurality of sub-data-sequence signals. A respective sub-data-sequence signal is outputted from a respective output of the demultiplexer. As used herein, the term xe2x80x9csub-data-sequence signalxe2x80x9d is a demultiplexed part of the encoded data.
The chip-sequence means outputs a plurality of chip-sequence signals, and the plurality of product devices, or exclusive-OR gates, multiplies each of the sub-data-sequence signals by a respective chip-sequence signal. Each of the chip-sequence signals is orthogonal or has low correlation to the other chip-sequence signals in the plurality of chip-sequence signals. At the output of the plurality of product devices is a plurality of spread-spectrum channels.
The combiner algebraically combines the plurality of spread-spectrum channels as a multichannel-spread-spectrum signal. The header device adds, i.e., concatenates, the multichannel-spread-spectrum signal to a header. The header device outputs a packet-spread-spectrum signal. The header later provides chip-sequence synchronization at the receiver. The transmitter subsystem amplifies and transmits at a carrier frequency the packet-spread-spectrum signal using radio waves over a communications channel.
A packet-spread-spectrum signal, as used herein, is a spread-spectrum signal transmitted by one or more packet transmitters, and arriving at the input of one or more packet receivers. The packet-spread-spectrum signal has the header concatenated with the multichannel-spread-spectrum signal. Timing for the present invention may be triggered from the header as part of the packet-spread-spectrum signal. For the case of the packet-spread-spectrum signal, each packet has the header followed in time by the multichannel-spread-spectrum signal. The header and multichannel-spread-spectrum signal are sent as the packet-spread-spectrum signal, and the timing for the multichannel-spread-spectrum signal, and thus the data, in the packet-spread-spectrum signal is keyed from the header. The data in the multichannel-spread-spectrum signal may contain information such as digitized voice, signaling, adaptive power control (APC), cyclic-redundancy-check (CRC) code, etc.
The header, or preamble, is generated from spread-spectrum processing a header-symbol-sequence signal with a chip-sequence signal. The multichannel-spread-spectrum signal part of the packet-spread-spectrum signal is generated from spread-spectrum processing a plurality of sub-data-sequence signals with the plurality of chip-sequence signals, respectively.
The chip-sequence signal used for the header and data is common to all users. The use of a common chip-sequence signal achieves low cost, since circuitry for changing chip-sequence signals is not required.
At each of the packet receivers, the translating device translates the packet-spread-spectrum signal from the carrier frequency to a processing frequency. The processing frequency may be at a radio frequency (RF), intermediate frequency (IF) or at baseband frequency. The processing frequency is a design choice, and any of the frequency ranges may be used by the invention. The header-matched filter detects the header in the packet-spread-spectrum signal. In response to detecting the header, the header-matched filter outputs a header-detection signal. The processor, in response to the header-detection signal, generates control and timing signals.
The plurality of data-matched filters despreads the multichannel-spread-spectrum signal embedded in the packet-spread-spectrum signal, as a plurality of received spread-spectrum channels. The multiplexer multiplexes the plurality of received spread-spectrum channels as received-encoded data. The decoder decodes the received-encoded data as received data. The receiver-FIFO memory stores the received data and outputs the received data to a data output. In an error-free environment, the received data are identical to the data input to the transmitter.
Another aspect of the present invention includes a packet-switched system comprising a plurality of packet transmitters that communicate with a plurality of packet receivers using radio waves. Each of the packet transmitters includes a transmitter-first-in-first-out (transmitter-FIFO) memory, an encoder, a demultiplexer, chip-sequence means, a first plurality of product devices, a first combiner, a first header device, a second plurality of product devices, a second combiner, a second header device, and a transmitter subsystem. Each packet receiver includes a translating device, a processor, a first plurality of data-matched filters, a second plurality of data-matched filters, a first plurality of header-matched-filter integrators, a second plurality of header-matched-filter integrators, a multiplexer, a decoder, and a receiver-first-in-first-out (receiver-FIFO) memory.
In the packet transmitter, the transmitter-FIFO memory stores data from a data input. The encoder encodes the data from the transmitter-FIFO memory as encoded data. The demultiplexer demultiplexes the encoded data into a first plurality of sub-data-sequence signals and a second plurality of sub-data-sequence signals. A respective sub-data-sequence signal is outputted from a respective output of the demultiplexer.
The chip-sequence means outputs a plurality of chip-sequence signals, and the first plurality of product devices and the second plurality of product devices, or exclusive-OR gates, multiplies each of the first plurality of sub-data-sequence signals and each of the second plurality of sub-data-sequence signals by a respective chip-sequence signal. Each of the chip-sequence signals used to multiply each of the first plurality of sub-data-sequence signals, is orthogonal or has low correlation to the other chip-sequence signals in the plurality of chip-sequence signals. The plurality of chip-sequence signals used with the first plurality of sub-data-sequence signals may be the same and used with the second plurality of sub-data-sequence signals. At the output of the first plurality of product devices is a first plurality of spread-spectrum channels, and at the output of the second plurality of product devices is a second plurality of spread spectrum channels.
The first combiner algebraically combines the first plurality of spread-spectrum channels as a first multichannel-spread-spectrum signal. The first header device adds, i.e., concatenates, the first multichannel-spread-spectrum signal to a first header. The first header device outputs a first packet-spread-spectrum signal. The first header later provides chip-sequence synchronization at the receiver.
The second combiner algebraically combines the second plurality of spread-spectrum channels as a second multichannel-spread-spectrum signal. The second header device adds, i.e., concatenates, the second multichannel-spread-spectrum signal to a second header. The second header device outputs a second packet-spread-spectrum signal. The second header later provides chip-sequence synchronization at the receiver. The transmitter subsystem amplifies and transmits, at a carrier frequency, the first packet-spread-spectrum signal and the second packet-spread-spectrum signal as a quadrature-amplitude modulated (QAM) signal, using spread-spectrum radio waves over a communications channel.
A QAM-spread-spectrum signal, as used herein, is a spread-spectrum signal transmitted by one or more packet transmitters, and arriving at the input of one or more packet receivers. The QAM-spread-spectrum signal has the first header and second header concatenated with the first multichannel-spread-spectrum signal and the second multichannel-spread-spectrum signal, respectively. Timing for the present invention may be triggered from the first and second headers as part of the QAM-spread-spectrum signal. For the case of the QAM-spread-spectrum signal, each packet has the first header followed in time by the first multichannel-spread-spectrum signal, and the second header followed in time by the second multichannel-spread-spectrum signal. The first and second headers and the first and second multichannel-spread-spectrum signals are sent as the QAM-spread-spectrum signal, and the timing for the multichannel-spread-spectrum signal, and thus the data, in the QAM-spread-spectrum signal is keyed from the first and second headers. The data in the first and second multichannel-spread-spectrum signals may contain information such as digitized voice, signalling, adaptive power control (APC), cyclic-redundancy-check (CRC) code, etc.
The first and second headers, or preambles, are generated from spread-spectrum processing a header-symbol-sequence signal with a chip-sequence signal. The first and second multichannel-spread-spectrum signal parts of the QAM-spread-spectrum signal are generated from spread-spectrum processing the first and second plurality of sub-data-sequence signals, respectively, with the plurality of chip-sequence signals.
The chip-sequence signal used for the first and second headers and data is common to all users. The use of a common chip-sequence signal achieves low cost, since circuitry for changing chip-sequence signals is not required.
At each of the packet receivers, the translating device translates the packet-spread-spectrum signal from the carrier frequency to a processing frequency. The processing frequency may be at a radio frequency (RF), intermediate frequency (IF) or at baseband frequency. The processing frequency is a design choice, and any of the frequency ranges may be used by the invention. The header-matched-filter integrator detects the first and second headers in the QAM-spread-spectrum signal. In response to detecting the first and second headers, the header-matched-filter integrator outputs a header-detection signal. The processor, in response to the header-detection signal, generates control and timing signals.
The first and second plurality of data-matched filters despread the first and second multichannel-spread-spectrum signals embedded in the QAM-spread-spectrum signal, as a first and second plurality of received spread-spectrum channels, respectively. The multiplexer multiplexes the first and second plurality of received spread-spectrum channels as received-encoded data. The decoder decodes the received-encoded data as received data. The receiver-FIFO memory stores the received data and outputs the received data to a data output. In an error-free environment, the received data are identical to the data input to the transmitter.
Additional objects and advantages of the invention are set forth in part in the description which follows, and in part are obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention also may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.